1. Field of the Invention
The present invention relates to a system and method for translating a high programming level languages code into a HDL code such as Verilog or VHDL, and more particularly, to a system and method for translating high programming level language codes into a HDL code, which is capable of accelerating applications by using a compiler backend to translate a high programming level language code, such as C, C++, Fortran or even Java, into a HDL (Hardware Description Language) code and logically synthesizing the HDL code in such a manner that it is cooperated with a main core.
2. Description of the Related Art
Digital circuit designs have been rapidly evolved over the past few decades. At an initial stage, digital circuits were designed using vacuum tubes and transistors, followed by integrated circuits (ICs) having logic gates integrated on one chip. Development of technologies has led to from SSI (Small Scale Integration) having a few number of logic gates, through MSI (Medium Scale Integration), to LSI (Large Scale Integration) having thousands of logic gates integrated on one chip. At this point of time, CAD (Computer Aided Design) technology has been required and developed. Chip designers have started to use logic simulation technologies in order to verify functions of blocks each having about 100 transistors, however, circuits have been still tested on breadboards and layouts have been drawn on paper or manually even with computers.
However, with further development to VLSI (Very Large Scale Integration) having about 100,000 transistors integrated on one chip, circuits become have been so complicated as not to be tested on breadboards any longer. Accordingly, computer-aided technologies have been essential to verification of VLSIs and P&R (Place and Routing) has also been automated by use of computers. Chip designers have designed a chip in the unit of small block at a logic gate level and designed up to a top-level block using small blocks and have introduced a logic simulator for function verification before the chip is actually fabricated.
Programming languages such as Fortran, Pascal, C and the like have been used to describe sequentially-operating computer programs for a long time. Similarly, digital circuit designers have felt the necessity of a standardized language to describe digital circuits, which results in HDL (Hardware Description Language). HDL can describe a concurrent procedure corresponding to hardware characteristics and may be represented by Verilog HDL and VHDL. Verilog HDL started from Gateway Design Automation and VHDL has been developed with support by DARPA (Defense Advanced Research Projects Agency).
Although HDL has often been used for logic verification, automated translation of circuit designs created by HDL into circuit diagrams expressed by logic gates has not been achieved. However, circuit design methods have made rapid progress with the advent of logic synthesis, thereby making it possible to design digital circuits at RTL (Register Transfer Level). That is, when a designer defined a data flow and process between registers, a logic synthesis tool could make connections between logic gates automatically.
Accordingly, HDL has played a leading role in digital circuit designs and circuit designers had no need to array and connect logic gates and draw circuit diagrams. Moreover, the use of HDL made it possible to make complicated designs by describing functions and data flows at abstraction levels.
However, as the complexity of electronic systems increases nowadays, there is an increasing need to describe the whole system at higher abstraction levels. Languages of such abstraction levels may include, for example, SystemC, SA-C, which are modeling languages of a system level, Fortran, C and C++, which are high programming level languages. When the whole system is described using such high level languages, hardware developers have a need to translate such high level languages into HDL codes such as Verilog HDL or VHDL. In addition, as software developers and hardware developers may make development with different languages, there is a problem that they have to perform system verification with tools of different levels.
For the purpose of overcoming such a problem, there are many previous researches about tools or methods of translating software level languages into HDL codes. However, there is a great difference between the programming concepts of hardware and software in translating high level language codes into HDL codes and so it is very difficult to express all software language syntaxes, such as pointer, two dimensional arrays and so on, in HDL languages. Accordingly, the conventional tools or methods have many limitations in that they can support only the translation from system level language codes, such as SystemC, SA-C, Streams-C and the like, into HDL codes, or even when some systems allow direct translation from high level languages into HDL, only a portion of high level language syntaxes can be directly translated.